In the development of VLSI device technology it has long been a desire to provide as many self-aligning features in a process as practical. Each self-aligned technology segment has the capability of reducing the required area taken by a combination of integrated circuit devices, thus increasing density as well as reducing the cost to manufacture components.
Traditionally, semiconductor processes utilize minimum definable dimensions only at the earliest process steps because, as the mask defining levels increase, alignment tolerances become cumulative and positioning of technology segments for proper alignment to lower levels requires the use of increased dimensions for each successive level. In many semiconductor processes 15 or more mask levels are required rendering the final metalization steps, or Back End Of the Line (BEOL), a limiting factor in obtaining greater VLSI densities.
Another factor effecting usable densities for BEOL technology has been that, as the number of process steps increase, the upper surface of the semiconductor substrate becomes more and more irregular or non-planar. In order to provide for adequate functional structures, larger dimensions were needed for contact via holes between different levels of interconnect metallurgy.
Recently it has become clear that in order to continue to provide increases in circuit density, improved techniques would be required. One of the improvements has been the development of techniques for achieving greater planarity in both metallurgy used for interconnects and its associated dielectric layers. For example, one planarization technique is that of Chemical-Mechanical, or Chem-Mech, Polishing (CMP) as described in greater detail in Beyer et al U.S. Pat. No. 9,944,836, issue Jul. 31, 1990, entitled "Chem-Mech Polishing Method for Producing Coplanar Metal/Insulator Films on a Substrate," based on application Ser. No. 791,860, filed Oct. 25, 1985 and assigned to the assignee of the instant application. CMP enables metal, dielectric or both to be planarized in order to reduce the processing and alignment tolerances required to fabricate high density devices.
High density BEOL processing has evolved from the use of a single layer of metal as both the interlevel via and interconnect to the use of separately definable via stud and line processing. Hazuki et al U.S. Pat. No. 4,582,563 issued Apr. 15, 1986 is an example of such technology in which a separate via stud is formed to act as the vertical interconnect and a substantially planar interconnect line is used for horizontal interconnects.
Another technique useful in reducing or eliminating alignment tolerances is that of providing self-aligning features in one or more mask levels. Several techniques are known to enable the formation of self-aligned studs and interconnecting lines. The article "Single Mask and Imaging for a Dual Level Self Aligned Definition," IBM Technical Disclosure Bulletin, December 1987, pp. 195-6 teaches a "studs up" self aligned technique. Chow et al U.S. Pat. No. 4,789,648 issued Dec. 6, 1988, entitled "Method for Producing Coplanar Multi-Level Metal Insulator Films on a Substrate and for Forming Patterned Conductive Lines Simultaneously with Stud Vias," and assigned to the assignee of the subject invention, the article "Single-Step, Multilevel, Metalization Technique for Conformal Wiring," IBM Technical Disclosure Bulletin, September 1988, pp. 400-1, and U.S. patent application Ser. No. 516,394 (BU9-89-025) by Cronin et al, filed Apr. 30, 1990, entitled "Process for Forming Multi-level Coplanar Conductor/Insulator Films Employing Photosensitive Polyimide Polymer Compositions" teach different techniques for forming self-aligned "studs down" interconnect metallurgy. Cronin et al U.S. Pat. No. 4,962,058 issue Oct. 9, 1990, entitled "A Multi-Level Integrated Circuit Wiring Structure from a Single Metal Deposit," and assigned to the assignee of the subject invention teaches a technique for forming both stud up and stud down structures. In each of the above references, both the stud and one of the interfacing layers of metallurgy are formed by a process in which a self-alignment between stud and line is achieved.
If circuit densities are to continue to increase, additional techniques are needed to further enhance BEOL technology.
It is therefore an object of this invention to provide substantial enhancement in the ability to obtain self-alignment for multiple levels of interconnect metallurgy by providing triple-level self-aligned metallurgy.
It is a further object to provide a process for achieving self-alignment between a first level of interconnect, a second level of interconnect, and their associated studs.